Dipl.-Inform. H. Gregor Molter Room: S2|02 A302 Phone: +49 6151 16-6692 molter@iss.tu-darmstadt.de

Research Interests

• Models of Computation for FPGAs
• Security in Embedded Systems

Publications

Books, Conferences, and Workshops

• Marc Stoettinger, H. Gregor Molter, and Sorin A. Huss
  Acceleration of Hypotheses Matrix Generation for DPA Attacks
  IEEE/ACM Design, Automation and Test in Europe, DATE'12, University Booth, Dresden Germany, March 2012
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• H. Gregor Molter and Sorin A. Huss
  The DEVS Model of Computation - A Foundation for a Novel Embedded Systems Design Methodology
  7th IEEE International Conference on Computer Engineering and Systems (ICCES'11), Page(s) xxi-xxvi, November 2011
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• H. Gregor Molter, André Seffrin, and Sorin A. Huss
  State Space Optimization within the DEVS Model of Computation for Timing Efficiency
  19th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'11), Hong Kong, China, Page(s) 422-427, October 2011
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• Abdulhadi Shoufan, Nico Huber, and H. Gregor Molter
  A Novel Cryptoprocessor Architecture for Chained Merkle Signature Scheme
  Microprocessors and Microsystems, Embedded Hardware Design, Elsevier, 35., Page(s) 34-47, February 2011
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• H. Gregor Molter, Marc Stoettinger, Abdulhadi Shoufan, and Falko Strenzke
  A Simple Power Analysis Attack on a McEliece Cryptoprocessor
  Journal of Cryptographic Engineering, 1., Page(s) 29-36, January 2011
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• Alexander Biedermann (Ed.) and H. Gregor Molter (Ed.)
  Design Methodologies for Secure Embedded Systems
  Springer, Berlin, Germany, ISBN: 978-3-64-216766-9, November 2010
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• Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, and Eike Kohnert
  A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem
  IEEE Transactions on Computers, 59., Page(s) 1133-1546, May 2010
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• Abdulhadi Shoufan, Falko Strenzke, H. Gregor Molter, and Marc Stoettinger
  A Timing Attack Against Patterson Algorithm in the McEliece PKC
  12th International Conference on Information Security and Cryptology (ICISC'09), Lecture Notes in Computer Science, December 2009
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• H. Gregor Molter, Felix Madlener, and Sorin A. Huss
  A System Level Design Flow for Embedded Systems based on Model of Computation Mappings
  4th IFAC Workshop on Discrete-Event System Design (DESDes'09), October 2009
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• H. Gregor Molter, André Seffrin, and Sorin A. Huss
  DEVS2VHDL: Automatic Transformation of XML-specified DEVS Model of Computation into Synthesizable VHDL Code
  12th IEEE Forum on Specification and Design Languages (FDL 2009), Sophia Antipolis, France, September 2009
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• H. Gregor Molter, Kei Ogata, Erik Tews, and Ralf-Philipp Weinmann
  An Efficient FPGA Implementation for an DECT Brute-Force Attacking Scenario
  5th IEEE International Conference on Wireless and Mobile Communications (ICWMC 2009), Page(s) 82-86, August 2009
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• Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, and Falko Strenzke
  A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
  20th IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2009
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• Felix Madlener, H. Gregor Molter, and Sorin A. Huss
  SC-DEVS: An efficient SystemC Extension for the DEVS Model of Computation
  ACM/IEEE Design Automation and Test in Europe (DATE'09), April 2009
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• H. Gregor Molter, Hui Shao, Henning Sudbrock, Sorin A. Huss, and Heiko Mantel
  Designing a Coprocessor for Interrupt Handling on an FPGA
  Modellierung und Analyse von Informationssystemen & Integrierte Schaltungen und Systeme, December 2008
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• Falko Strenzke, Erik Tews, H. Gregor Molter, Raphael Overbeck, and Abdulhadi Shoufan
  Side Channels in the McEliece PKC
  Int. Workshop on Post-Quantum Cryptography (PQCrypto 2008), Lecture Notes in Computer Science, 5299/2008, Page(s) 216-229, October 2008
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• H. Gregor Molter
  Kryptographischer Coprozessor für Server: Effiziente und flexible Multi-Core-Architektur für Server als System-on-a-Chip
  VDM Verlag Dr. Müller, ISBN: 978-3-63-905437-8, August 2008
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• Ralf Laue, H. Gregor Molter, Felix Rieder, Kartik Saxena, and Sorin A. Huss
  A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications
  IEEE Computer Society Annual Symposium on VLSI, April 2008
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Diploma Thesis

• H. Gregor Molter
  Flexibler Krypto-CoProzessor für Server als SoC
  Slides: Part 1 and Part 2 (both in german)

Book

Finished Student Theses

• Kiril Nastev
  Development of a Compiler for the DEVS Processor Platform
  Bachelorarbeit, Januar 2012
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• Johannes Kohlmann
  Generierung eingebetteter Systeme aus DEVS-Modellen
  Masterarbeit, April 2011
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• Nabil Sayegh
  Sichere Kommunikation in eingebetteten Systemen am Beispiel eines Quadrokopters
  Diplomarbeit, Juni 2010
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• Steven Arzt, Daniel Münch, Gregor Rynkowski, Alexander Spitzl
  Beschleunigte Hypothesenberechnung für Power-Analysis-Attacken
  Bachelorpraktikum, April 2010
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• Martin Feldmann
  Kryptographischer Coprozessor für Serversysteme: Effiziente und flexible Multi-Core-Architektur als System-on-a-Chip inklusive OpenSSL Integration
  Masterarbeit, CASED, Februar 2010
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• Yanmin Guo
  DEVS Modell Editor für SystemC Simulation
  Diplomarbeit, Januar 2010
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• Andre Seffrin
  VHDL Generator für DEVS Modelle
  Diplomarbeit, Mai 2009
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• Nico Huber, Eike Kohnert, Robert Mahs
  Quantenresistente Kryptograhieverfahren
  Forschungsarbeit, März 2009
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• Nico Huber
  Quantenresistente Kryptograhieverfahren: Entwurf und Implementierung einer Hardware-Architektur des Merkle-Signaturverfahrens
  Bachelorarbeit, Februar 2009
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• Kei Ogata
  Implementierung eines Brute-Force-Kodebrechers
  Diplomarbeit, Januar 2009
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• Thorsten Wink
  Quantenresistente Kryptograhieverfahren
  Diplomarbeit, Januar 2009
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• Hui Shao
  Designing a Coprocessor for Interrupt Handling on an FPGA
  Forschungsarbeit, Dezember 2008
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• Michael Schaffner
  Implementierung eines Buffers in VHDL
  Externes Praktikum, Juli 2007
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